The present invention relates to a codec which converts an analog signal to a digital signal, and converts a digital signal into an analog signal, and in particular to a codec of a single channel type comprising switched-capacitor filters, an analog-to-digital converter (an A/D converter) and a digital-to-analog converter (a D/A converter).
The codecs can be used, for example, being disposed in a digital terminal equipment, such as a digital telephone set, a digital PBX (private branch exchange) and a PCM multiplexer, connected to a communication network, for communication with another digital terminal equipment.
A conventional technology relating to a codec is shown in the following publication:
"Keys to design anti application of A/D and D/A converters" The First Edition (May 31, 1985); by Nihon Kogyou Gijutsu Center; pages 177 to 180.
FIG. 6 is a block diagram showing an example of a conventional codec shown in the above publication.
Provided at the coding section CS of the codec are a coding controller 14 which controls the coding section, a coding PLL (phase-locked loop) circuit 11 generating a plurality of high-speed clock signals on the basis of a coding sync signal SYa supplied from the outside, e.g., from a communication network, and a coding filter 12, which is configured of switched capacitors, filters an analog signal Ai, e.g., a speech signals input from the outside, e.g., from a transmitter part (microphone) of a telephone set, operating in synchronism with a high-speed clock signal supplied from the coding PLL circuit 11. An A/D converter 13 converts the output of the coding filter 12 into a digital signal in the form of parallel data, in synchronism with the high-speed clock signals supplied from the coding PLL circuit 11. The digital signal is then sent to the coding controller 14, which converts the parallel data from the A/D converter 13 into serial data Do. Each sample of the analog signal is digitized into a byte of digital signal consisting of eight bits. Each byte of the serial data Do of eight bits is then sent out, in synchronism with the coding clock signal CKa.
The coding controller 14 receives the coding sync signal SYa of 8 kHz, for example, which serves as a time reference for the sampling at the A/D converter 13, and the coding clock signal CKa used as a shift clock for determining the output speed or rate of the digital signal output, and controls the coding filter 12 and the A/D converter 18. The coding clock signal CKa is set at a frequency several times the coding sync signal SYa, and is normally within in the range off 64 kHz to 2048 kHz, and is determined in accordance with the terminal equipments that are connected to the communication network.
Provided at the decoding section DS of the codec are a decoding PLL circuit 21 for receiving a decoding sync signal SYb of a reference frequency supplied from the outside, e.g., from the communication network, and a decoding clock signal CKb, and a decoding controller 22 receiving the decoding sync signal SYb, the decoding clock signal CKb, and a digital signal Di in the form of serial data, from the communication network. Each byte of serial data consisting of eight bits is supplied in synchronism with each decoding sync signal SYb. The decoding sync signal SYb is used as a time reference for the D/A conversion at a D/A converter 23, and is set for example at 8 kHz. The decoding clock signal CKb has the same data speed as the input digital signal Di, and is used as a shift clock for inputting the digital signal into the codec, and is set at a frequency several times the frequency of the decoding sync signal SYb, and is normally within the range of 64 kHz to 2048 kHz, and is determined in accordance with the terminal equipments that are connected to the communication network.
The decoding PLL circuit 21 generates a plurality of high-speed clock signals on the basis of the decoding sync signal SYb supplied from the outside, e.g., from the communication network. The decoding controller 22 controls the decoding section, and reads the digital signal Di in the form of serial data, in synchronism with the decoding clock signal CKb, and converts the digital data in the form of serial data, into parallel data. The D/A converter 28 converts the digital signal, into an analog signal, in synchronism with the high-speed clock signal supplied from the decoding PLL circuit 21.
A decoding filter 24 is configured of switched capacitors, and operates in synchronism with the high-speed clock signal supplied from the decoding PLL circuit 21, to filter the output of the D/A converter 23, and outputs an output analog signal Ao.
The operation is next described.
When the coding clock signal CKa and the coding sync signal SYa are input to the coding section, the coding PLL circuit 11 and the coding controller 14 begin operating, and the coding filter 12, under the control by the coding controller 14, filters the analog signal Ai to be transmitted. The filtered analog signal is converted by the the A/D converter 13, also controlled by the coding controller 14, into a digital signal, and is sent to the coding controller 14. The coding controller 14 transmits the digital signal Do from the A/D converter 13 to the outside, in synchronism, with the coding clock signal CKa.
When the decoding clock signal CKb and the decoding sync signal SYb are input to the decoding section, the decoding controller 22 begins operating. The decoding controller 22 reads the digital signal Di in synchronism with the decoding clock signal CKb. When each byte of the digital signal Di has been read, the decoding PLL circuit 21 begins operating, and the D/A converter 23 and the decoding filter 24 are controlled by the outputs of the decoding PLL circuit 21. The D/A converter 23 converts the digital signal Di read by the decoding controller 22, into an analog signal. The analog signal is filtered by the decoding filter 24, and the filtered analog signal Ao is output.
As described above, the coding PLL circuit 11 begins operating when the coding sync signal SYa is input, and the decoding PLL circuit 21 begins operating when the digital data Di is read into the codec. Since the coding section and the decoding section operate with independent timings, the coding PLL circuit 11 and the decoding PLL circuits 21 are provided separately at the coding and decoding sections. With regard to the high-speed clock signals used for the coding filter 12 and the decoding filter 24, the clock signal for the coding filter 12 must be in synchronism with the A/D conversion, and the clock signal for the decoding filter 24 must be in synchronism with the D/A conversion. This is to avoid noises which occur when the clocks are asynchronous. For this reason, the clocks generated separately at the coding PLL circuit 11 and the decoding PLL circuit 21 are used in the respective circuits.
The codec of the above configuration has the following problems.
As a result of furtherance of synchronization of the communication systems, a common clock signal is often used for the coding clock signal CKa and the decoding clock signal CKb. However, with the conventional codec, even if a common signal is used for the coding and decoding clock signals CKa and CKb, and for the coding and decoding sync signals SYa and SYb, the operation timings at the coding and decoding sections differ depending on the frequency of the clocks, and it is therefore necessary to provide the separate coding PLL circuit 11 and decoding PLL circuit 21. This is because the codec must be so designed to operate with any of various clock frequencies as the devices in which the codec is incorporated may use different frequencies. For instance, digital telephone sets may use 64 kHz, PCM multiplexers may use 1544 kHz, and digital PBX may use 2048 kHz.
Where two PLL circuits 11 and 21 are present in the coding and decoding sections, the clock signal generated by the decoding PLL circuit 21 is an asynchronous clock as seen from the coding section, and the clock signal generated by the coding PLL circuit 11 is an asynchronous clock as seen from the decoding section. As a result, noises are increased, so that the S/N ratio (signal-to-noise ratio) is degraded. Moreover, the circuits of the coding PLL circuit 11 and the decoding PLL circuit 21 are complex and bulky, so where the codec is formed or implemented in a semiconductor integrated circuit, the area required on the integrated circuit chip is large, and the power consumption is large because of the oscillating function provided.